
module DIVN_CNTR_DW01_inc_0 ( A, SUM );
  input [6:0] A;
  output [6:0] SUM;
  wire   carry_6_, carry_5_, carry_4_, carry_3_, carry_2_;

  HAX1 U1_1_5 ( .A(A[5]), .B(carry_5_), .YC(carry_6_), .YS(SUM[5]) );
  HAX1 U1_1_4 ( .A(A[4]), .B(carry_4_), .YC(carry_5_), .YS(SUM[4]) );
  HAX1 U1_1_3 ( .A(A[3]), .B(carry_3_), .YC(carry_4_), .YS(SUM[3]) );
  HAX1 U1_1_2 ( .A(A[2]), .B(carry_2_), .YC(carry_3_), .YS(SUM[2]) );
  HAX1 U1_1_1 ( .A(A[1]), .B(A[0]), .YC(carry_2_), .YS(SUM[1]) );
  XOR2X1 U1 ( .A(carry_6_), .B(A[6]), .Y(SUM[6]) );
  INVX1 U2 ( .A(A[0]), .Y(SUM[0]) );
endmodule


module DIVN_CNTR ( reset, N, DCO_CLK_IN, DCO_CLK );
  input [6:0] N;
  input reset, DCO_CLK_IN;
  output DCO_CLK;
  wire   N17, N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30,
         n8, n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22,
         n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36,
         n37;
  wire   [6:0] count;

  DFFSR count_reg_0_ ( .D(N24), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[0]) );
  DFFSR count_reg_1_ ( .D(N25), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[1]) );
  DFFSR count_reg_2_ ( .D(N26), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[2]) );
  DFFSR count_reg_3_ ( .D(N27), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[3]) );
  DFFSR count_reg_4_ ( .D(N28), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[4]) );
  DFFSR count_reg_5_ ( .D(N29), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[5]) );
  DFFSR count_reg_6_ ( .D(N30), .CLK(DCO_CLK_IN), .R(n8), .S(1'b1), .Q(
        count[6]) );
  INVX1 U9 ( .A(reset), .Y(n8) );
  AND2X1 U11 ( .A(N23), .B(n10), .Y(N30) );
  AND2X1 U12 ( .A(N22), .B(n10), .Y(N29) );
  AND2X1 U13 ( .A(N21), .B(n10), .Y(N28) );
  AND2X1 U14 ( .A(N20), .B(n10), .Y(N27) );
  AND2X1 U15 ( .A(N19), .B(n10), .Y(N26) );
  AND2X1 U16 ( .A(N18), .B(n10), .Y(N25) );
  AND2X1 U17 ( .A(N17), .B(n10), .Y(N24) );
  OR2X1 U18 ( .A(n11), .B(n12), .Y(n10) );
  NAND3X1 U19 ( .A(count[5]), .B(count[4]), .C(count[6]), .Y(n12) );
  NAND3X1 U20 ( .A(count[3]), .B(count[2]), .C(n13), .Y(n11) );
  AND2X1 U21 ( .A(count[0]), .B(count[1]), .Y(n13) );
  OAI21X1 U22 ( .A(n14), .B(n15), .C(n16), .Y(DCO_CLK) );
  NAND3X1 U23 ( .A(n17), .B(n18), .C(n19), .Y(n16) );
  NOR2X1 U24 ( .A(N[3]), .B(N[0]), .Y(n19) );
  OAI21X1 U25 ( .A(N[6]), .B(n20), .C(n21), .Y(n18) );
  NAND3X1 U26 ( .A(N[6]), .B(count[6]), .C(n22), .Y(n21) );
  NOR2X1 U27 ( .A(N[5]), .B(N[4]), .Y(n22) );
  AOI22X1 U28 ( .A(n23), .B(N[5]), .C(n24), .D(N[4]), .Y(n20) );
  NOR2X1 U29 ( .A(N[5]), .B(n25), .Y(n24) );
  INVX1 U30 ( .A(count[4]), .Y(n25) );
  AND2X1 U31 ( .A(n26), .B(count[5]), .Y(n23) );
  NAND2X1 U32 ( .A(n27), .B(n26), .Y(n15) );
  INVX1 U33 ( .A(N[4]), .Y(n26) );
  OAI21X1 U34 ( .A(N[3]), .B(n28), .C(n29), .Y(n27) );
  NAND3X1 U35 ( .A(N[3]), .B(n17), .C(n30), .Y(n29) );
  AND2X1 U36 ( .A(n31), .B(count[3]), .Y(n30) );
  AOI22X1 U37 ( .A(n32), .B(N[0]), .C(n33), .D(n31), .Y(n28) );
  INVX1 U38 ( .A(N[0]), .Y(n31) );
  OAI21X1 U39 ( .A(n34), .B(n35), .C(n36), .Y(n33) );
  NAND3X1 U40 ( .A(count[2]), .B(n34), .C(N[2]), .Y(n36) );
  NAND2X1 U41 ( .A(count[1]), .B(n37), .Y(n35) );
  INVX1 U42 ( .A(N[2]), .Y(n37) );
  INVX1 U43 ( .A(N[1]), .Y(n34) );
  AND2X1 U44 ( .A(count[0]), .B(n17), .Y(n32) );
  NOR2X1 U45 ( .A(N[1]), .B(N[2]), .Y(n17) );
  OR2X1 U46 ( .A(N[5]), .B(N[6]), .Y(n14) );
  DIVN_CNTR_DW01_inc_0 add_39 ( .A(count), .SUM({N23, N22, N21, N20, N19, N18, 
        N17}) );
endmodule

